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author | tomsmeding <tom.smeding@gmail.com> | 2019-04-28 16:49:32 +0200 |
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committer | tomsmeding <tom.smeding@gmail.com> | 2019-04-28 16:49:32 +0200 |
commit | b2320404202ad3296480bd472a6a79f5e5427de8 (patch) | |
tree | 22f37cbabbf95b864db3fcf3761c4372cd7b81e4 /Intermediate.hs | |
parent | 3c40705b60d40f4c863c72091b3b4f30ff79c916 (diff) |
Preliminary finish of lowering
That is to say, there is no register allocation yet, but I think the
currently generated code can be regalloc'd without much trouble.
Diffstat (limited to 'Intermediate.hs')
-rw-r--r-- | Intermediate.hs | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Intermediate.hs b/Intermediate.hs index 2729493..8c4a5dc 100644 --- a/Intermediate.hs +++ b/Intermediate.hs @@ -46,6 +46,8 @@ data InsCode | IDiscard Ref -- | Do stuff on function entry | IFunctionEntry + -- | Do stuff on application entry + | IApplicationEntry deriving Eq data Terminator @@ -98,6 +100,7 @@ instance Show InsCode where show (IAllocClo name vs) = "alloc-closure \"" ++ name ++ "\" " ++ show vs show (IDiscard r) = "discard " ++ show r show IFunctionEntry = "function-entry" + show IApplicationEntry = "application-entry" instance Show Terminator where show (IBr r b1 b2) = "br " ++ show r ++ " " ++ show b1 ++ " " ++ show b2 |